Espressif Systems /ESP32-C2 /SPI0 /CTRL

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Interpret as CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (FDUMMY_OUT)FDUMMY_OUT 0 (FCMD_DUAL)FCMD_DUAL 0 (FCMD_QUAD)FCMD_QUAD 0 (FASTRD_MODE)FASTRD_MODE 0 (FREAD_DUAL)FREAD_DUAL 0 (Q_POL)Q_POL 0 (D_POL)D_POL 0 (FREAD_QUAD)FREAD_QUAD 0 (WP)WP 0 (FREAD_DIO)FREAD_DIO 0 (FREAD_QIO)FREAD_QIO

Description

SPI0 control register.

Fields

FDUMMY_OUT

In the dummy phase the signal level of spi is output by the spi controller.

FCMD_DUAL

Apply 2 signals during command phase 1:enable 0: disable

FCMD_QUAD

Apply 4 signals during command phase 1:enable 0: disable

FASTRD_MODE

This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable.

FREAD_DUAL

In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.

Q_POL

The bit is used to set MISO line polarity, 1: high 0, low

D_POL

The bit is used to set MOSI line polarity, 1: high 0, low

FREAD_QUAD

In the read operations read-data phase apply 4 signals. 1: enable 0: disable.

WP

Write protect signal output when SPI is idle. 1: output high, 0: output low.

FREAD_DIO

In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.

FREAD_QIO

In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.

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